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gm76c8128cl/cll 131,072 words x 8 bit cmos static ram description features * fast speed : 55/70/85ns * low power standby and low power operation standby : 0.275mw max. at t a = - 40 ~ 85c(lle/lli) 0.55mw max. at t a = - 40 ~ 85c(le/li) 0.11mw max. at t a = 0 ~ 70c(ll) 0.55mw max. at t a = 0 ~ 70c(l) operation : 385mw (max) * completely static ram : no clock or timing strobe required * equal access and cycle time * ttl compatible inputs and outputs * capability of battery back-up operation * single + 5v+/-10% operation * standard 32 dip, sop and tsop-i,stsop-i * temperature range commercial(0 ?- 70c) : gm76c8128c extended (-25 ~ 85c) : gm76c8128c-e industrial (-40 ~ 85c) : gm76c8128c-i the gm76c8128cl/cll is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits. using a 0.6 u m advanced cmos technology and it provides high speed operation with minimum cycle time of 55/70/85ns. the device is placed in a low power standby mode with /cs1 high or cs2 low and the output enable (/oe) allows fast memory access. thus it is suitable for high speed and low power applications, especially where battery back-up is required. 85 pin description i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 pin function a0-a16 address inputs i/o0-i/o7 v cc v ss write enable input chip select input output enable input data inputs/outputs power supply (4.5v ~5.5v) ground nc no connection /we /cs1, cs2 /oe pin configuration (top view) a7 a6 a5 a4 a3 a2 a1 a0 v cc a15 cs2 /we a13 a8 a9 a11 /oe a10 /cs1 i/o7 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 24 25 26 27 28 29 30 31 32 i/o0 i/o1 i/o6 i/o5 13 14 19 20 i/o2 v ss i/o4 i/o3 15 16 17 18 nc a16 a14 a12 block diagram memory cell array 1024 x 128 x 8 (128k x 8) column select i/o buffer address buffer x decoder 10 1024 7 128 128 x 8 8 y decorder /cs1, cs2 a0 a1 a2 a14 a15 a16 /cs1 /oe . . . . . . . . chip control /oe, /we chip control /we cs2 lg semicon co.,ltd.
gm76c8128cl/cll 86 absolute maximum ratings* *: stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions (t a = - 40 ~ 85c) truth table *note: x means don't care /cs1 l l l cs2 h h h /oe l x h a0 to a16 stable stable stable data i/o output data input data hi-z mode read write output disable h x x - hi-z standby x l x - hi-z /we h l h x x symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 5.5 v cc + 0.3 0.8 typ 5.0 - - min 4.5 2.2 -0.3* *note :v il (min) = -3.0v for <= 10ns pulse symbol parameter rating unit t a t stg t sol -25 ~ 85 -55 ~ 150 260, 10 (at lead) ambient temperature under bias storage temperature soldering temperature and time c c c, s v cc -0.3 ~ 7.0 supply voltage v v in v i/o -0.5 ~ v cc + 0.5 input voltage input and output voltage v v p d 1.0 power dissipation w c c -40 ~ 85 0 ~ 70 gm76c8128c-e gm76c8128c-i gm76c8128c capacitance (f = 1mh z , t a = 25c) symbol parameter unit c in c i/o input capacitance output capacitance pf pf max 6 8 min test conditions v i = 0v v o = 0v - - *note: this parameter is sampled and not 100% tested. -0.3 ~ 7.0
gm76c8128cl/cll 87 dc operating characteristics (v cc = 5v+/-10%, t a = - 40 ~ 85c) *typ. values are measured at 25c symbol parameter i i(l) input leakage current i o(l) output leakage current v oh high level output voltage v ol low level output voltage i cc operating supply current i cc1 average operating current i cc2 i ccs1 i ccs2 standby current(ttl) conditions v in = 0 to v cc /cs1 = v ih or cs2 = v il /oe = v ih , v ss <=v out <=v cc i oh = -1.0ma i ol = 2.1ma /cs1 = v il and cs2 = v ih v in = v ih /v il, i out = 0ma /cs1 = v il and cs2 = v ih v in = v ih /v il i out = 0ma t cycle = min, cycle /cs1 = 0.2v, cs2 = v cc -0.2v v in = v cc - 0.2v/0.2v i out = 0ma t cycle = 1 u s /cs1 = v ih , cs2 = v il /cs1 = v cc -0.2v cs2 = 0.2v unit ua ua v v ma ma ma ma max 1 1 - 0.4 15 70 10 2 *typ - - - - - min -1 -1 2.4 - - - - - ua ua 100 50 - - - - - - - - - gm76c8128c-e gm76c8128c-i gm76c8128c standby current(cmos) 100 20 - - l - version ll - version l - version ll - version test conditions (v cc = 5v+/-10%, t a = - 40 ~ 85c, unless otherwise noted.) ac operating characteristics parameter input pulse level input rise and fall time value 0.6v to 2.4v 5ns input and output timing reference levels 1.5v output load see below output load (a) output load (b) (for tchz, tclz, twhz, tow, tolz & tohz) +5v d out 1.8k ? 990 ? 5 ? * +5v d out 1.8k ? 990 ? 100 ? *
gm76c8128cl/cll 88 ac operating characteristics (v cc = 5v+/-10%, t a = - 40 ~ 85c) symbol parameter unit t rc read cycle time t aa address access time t acs1 chip select 1 access time t acs2 chip select 2 access time t oe output enable access time t clz1 chip select 1 output setup time t chz1 chip select 1 output floating t clz2 chip select 2 output setup time t chz2 chip select 2 output floating t olz output enable output setup time t ohz output enable output floating t oh output hold time max min ns ns ns ns ns ns ns ns ns ns ns ns - 85 85 85 45 - 30 - 30 - 30 - 85 - - - - 10 - 10 - 0 - 10 - 55 55 55 30 - 20 - 20 - 20 - 55 - - - - 5 - 5 - 0 - 5 write cycle symbol parameter unit t wc write cycle time t cw1 chip select time 1 t cw2 chip select time 2 t aw address enable time t as address setup time t wp write pulse width t wr address hold time t dw input data setup time t dh input data hold time t whz write to output in high-z t ow output active from end of write max min ns ns ns ns ns ns ns ns ns ns ns - 85 - 55 - 50 50 50 0 0 0 0 45 25 20 - - - - - - - - - - 75 75 70 0 0 0 0 60 35 30 - - - - - - - - - read cycle max min max min max min max min - 70 70 70 35 - 25 - 25 - 25 - 70 - - - - 5 - 5 - 0 - 10 - 70 - 65 65 60 0 0 0 0 50 30 25 - - - - - - - - - gm76c8128c-55 gm76c8128c-70 gm76c8128c-85 gm76c8128c-55 gm76c8128c-70 gm76c8128c-85
gm76c8128cl/cll 89 timing waveforms /cs1 cs2 t rc add t aa t chz1 t ohz /oe t acs1 t clz1 t acs2 t clz2 t oe t olz t chz2 t oh d out valid data high-z read cycle (note 1)
gm76c8128cl/cll write cycle (1) (/we controlled) (notes 2, 3, 4) /cs1 t wc d out add cs2 t as /we t ow d in valid data t aw t wr t wp t cw1 t cw2 t whz t dw t dh 90
gm76c8128cl/cll write cycle (2) (/cs1 controlled) (notes 4) /we t wc d out add /cs1 t as d in valid data t wr t wp t cw2 t dw t dh t cw1 t whz t clz cs2 91
gm76c8128cl/cll /we t wc d out add cs2 t as write cycle (3) (cs2 controlled) (notes 4) d in valid data t wr t wp t dw t dh t whz t clz t cw1 /cs1 notes: 1. /we is high for read cycle. 2. assuming that /cs1 low transition or cs2 high transition occurs coincident with or after /we low transition. outputs remain in a high impedance state. 3. assuming that /cs1 high transition or cs2 low transition occurs coincident with or prior to /we high transition. outputs remain in a high impedance state. 4. assuming that /oe is high for write cycle. outputs are in a high impedance state during this period. t cw2 92
gm76c8128cl/cll * 3 u a max at t a = 0 ~ 40c ** trc = read cycle notes: in data retention mode, cs2 controls the address, /we, /cs1, /oe and d in buffer. if cs2 controls data retention mode, v in for these inputs can be in the high impedance state. if /cs1 controls the data retention mode, cs2 must satisfy either cs2 v ccr - 0.2v or cs2<=0.2v. the other input levels (address, /we, /oe, i/o) can be in the high impedance state. > _ * low v cc data retention mode: (1) /cs1 controlled v cc data retention mode t cdr t r /cs1 >= v ccr - 0.2v 4.5v 2.2v v ccr1 /cs1 0v * low v cc data retention mode: (2) cs2 controlled v cc data retention mode t cdr t r cs2 <= 0.2v 4.5v cs2 v ccr2 0.4v 0v 93 data retention characteristics symbol parameter unit v ccr i ccr data retention supply voltage data retention current u a max typ min vcc=3.0v chip select to data retention time l - version ll - version operation recovery time t cdr t r 2.0 - 5.5 v - - 1 0.5 50 15* 0 t rc ** - - - - ns ns l - version ll - version - - - - 50 25* gm76c8128c-e gm76c8128c-i gm76c8128c
gm76c8128cl/cll 94 package dimensions unit: inches (mm) 32 sop 0.435(11.05) min 0.445(11.30) max 0.020(0.50) max 0.014(0.35) min typ 0.050(1.27) 0.010(0.254) max 0.004(0.102) min 0.010(0.254) max 0.004(0.10) min 0.55(14.05) min 0.57(14.40) max 0.04(1.04) max 0.02(0.53) min 0.090(2.29) max 0.086(2.18) min 0.799(20.30) min 0.815(20.70) max 0 ~ 8 32 dip 0.190(4.83) max 0.165(4.191) min typ 0.100(2.54) 0.020(0.51) max 0.016(0.41) min 0.540(13.72) typ 1.665(42.29) max 1.645(41.78) min 0.045(1.14) min 0.055(1.40) max 0.15(3.81) 0.015(0.38) 0.135(3.43) max 0.125(3.18) min 0.600(15.24) min 0.625(15.88) max 0.600(15.240) 0 ~ 15 o 0.015(0.380) max 0.008(0.200) min typ typ min
gm76c8128cl/cll 95 0.000(0.00) max 0.006(0.15) min 0.313(7.95) min 0.327(8.30) max 0.795(20.20) max 0.780(19.80) min 0.047(1.2) max 0.039(1.0) min 0.020(0.50) 0.006(0.15) min 0.010(0.25) max 32 tsop i (8x20mm) 0.728(18.50) max 0.720(18.30) min 0.024(0.60) max 0.016(0.40) min typ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 /we cs2 a15 vcc n.c a16 a14 a12 a7 a6 a5 a4 /oe a10 /cs1 i/o7 i/o6 i/o5 i/o4 i/o3 vss i/o2 i/o1 i/o0 a0 a1 a2 a3 32small tsop-i(8x13.4mm) 0.006(0.15) max 0.002(0.05) min 0.311(7.95) min 0.320(8.2) max 0.020(0.5) 0.006(0.15) min 0.009(0.25) max typ 0.467(11.86) max 0.461(11.70) min 0.044(1.0) max 0.035(1.2) min 0.019(0.4) max 0.020(0.6) min 0.528(13.50) max 0.527(13.30) min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 /we cs2 a15 vcc n.c a16 a14 a12 a7 a6 a5 a4 /oe a10 /cs1 i/o7 i/o6 i/o5 i/o4 i/o3 vss i/o2 i/o1 i/o0 a0 a1 a2 a3

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